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#      * Redistributions of source code must retain the above copyright
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#include "compliance_test.h"
#include "compliance_model.h"

RVTEST_ISA("RV32IF")

# Test Virtual Machine (TVM) used by program.


# Test code region.
RVTEST_CODE_BEGIN

    RVMODEL_IO_INIT
    RVMODEL_IO_ASSERT_GPR_EQ(x31, x0, 0x00000000)
    RVMODEL_IO_WRITE_STR(x31, "# Test Begin\n")

    # ---------------------------------------------------------------------------------------------
    RVTEST_CASE(1,"check ISA:=regex(.*I.*); \
                        def TEST_CASE_1=True")
    RVMODEL_IO_WRITE_STR(x31, "#Test-1 check floats count\n");
    
    # initialize 
    li t2, 1
    csrwi EVENT_REG, 7    
    csrw COUNTER_REG, x0
    la t3, test_data
   
#if __riscv_xlen == 64
    fcvt.l.s t5, ft4          
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fcvt.lu.s t5, ft4          
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fcvt.s.l ft5, t4          
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fcvt.s.lu ft5, t4          
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

#endif
    #flw ft5, 4(t3)          
    #csrr t0, COUNTER_REG
    #bne t0, t2, fail

    #addi t2, t2, 1

    #fsw ft5, (t3)          
    #csrr t0, COUNTER_REG
    #bne t0, t2, fail

    #addi t2, t2, 1

    fmadd.s ft5, ft5, ft5, ft4          
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fmsub.s ft10, ft4, fs2, ft0 
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fnmsub.s ft0, fa1, fa1, fs5  
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fnmadd.s ft0, fa1, fa1, fs5  
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fadd.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fsub.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fsub.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fsub.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fmul.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fdiv.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fsqrt.s ft8, fs2       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fsgnj.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fsgnjn.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fsgnjx.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fmin.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fmax.s ft0, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fcvt.wu.s t4, ft10             
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fcvt.w.s t5, ft11             
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fmv.x.w t4, fs3       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    feq.s t4, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    flt.s t4, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fle.s t4, fs3, ft1       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fclass.s t4, fs3       
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fcvt.s.wu ft0, t4             
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fcvt.s.w ft0, t4             
    csrr t0, COUNTER_REG
    bne t0, t2, fail

    addi t2, t2, 1

    fmv.w.x ft0, t4             
    csrr t0, COUNTER_REG
    bne t0, t2, fail
  pass:
    RVMODEL_IO_WRITE_STR(x31, "#Test-1 Passed\n");
    j HALT
  fail:
    RVMODEL_IO_WRITE_STR(x31, "#Test-1 Failed\n");
    j HALT

 # ---------------------------------------------------------------------------------------------
  HALT:
    RVMODEL_HALT

RVTEST_CODE_END

# Input data section.
    .data

test_data:
    .dword 0

# Output data section.
RVMODEL_DATA_BEGIN


RVMODEL_DATA_END
